Actuator drive circuitry for producing dual level drive current

ABSTRACT

Drive circuitry for a bi-directional solenoid actuator having first and second coils which are energized during mutually exclusive and complementary time periods. Each coil is in circuit with a low impedance bypass which is effective only for a short time after energization of the associated coil. While the bypass is effective, a relatively high current is applied to the coil to seat the solenoid core. When the bypass is rendered ineffective, a relatively lower current is applied to the coil to hold the core in place. The circuitry also includes normally back-biased diodes which are driven to a forward-biased state upon coil deenergization to connect voltage sources to the coil to limit induced voltages to accelerate current decay in the de-energized coil.

United States Patent 1 [111 3,766,432 Markowitz et al. a Oct. 16, 1973[54] ACTUATOR DRIVE CIRCUITRY FQR 3,624,417 11/1971 Dao 307/270PRODVCING A LEVEL DRIVE 3,729,655 4/1973 Gratzke 3l7/DIG. 6 i CURRENTPrimary Examiner-John S. Heyman [75] Inventors: Ivan N. Markowitz;Ernest Paul Lee, AttorneyFred Jacob et al.

both of Oklahoma City, Okla. {73] Assignee: Honeywell InformationSystems ABSTRACT Inc., Waltham, Mass. Drive circuitry for abi-directional solenoid actuator 22] Filed I I ()et 1 972 having firstand second coils which are energized during mutually exclusive andcomplementary time peri [21] App]. No.: 299,554 ods. Each coil is incircuit with a low impedance bypass which is effective only for a shorttime after energization of the associated coil. While the bypass is ef-2 fill/DIG .05; 0 6 fective, a relatively high current is applied to thecoil [51] Int Cl H611] 47/22 to seat the solenoid core. When the bypassis rendered [58] Fieid 139 155 5 ineffective, a relatively lower currentis applied to the 1, 4 coil to hold the core in place. The circuitryalso ini cludes normally back-biased diodes which are driven [56]References Cited to a forward-biased state upon coil de-energization to1 connect voltage sources to the coil to limit induced UNITED STATESPATENTS voltages to accelerate current decay in the de 2,951,186 8/1960Dickinson 317/DIG. 6 enef ized coil 3,210,570 10/1965 Brock et al.317/137 X g 6 Claims, 2 Drawing Figures T-50 z? 5W/7'CH c/Pcu/r 7 6 aimZ4 4g SW/I'CH LOW 2' CIRCUIT 51 5455 5 /6 3 4 Z8 d4 M/l/ 0 1 91%? ANDPULSE- AND SHAPE? 1- SW/TCH LOW z C/PCU/T BYPASS 54 4a sw/rcH C/PCU/TACTUATOR DRIVE CIRCUITRY FOR PRODUCING DUAL LEVEL DRIVE CURRENTBACKGROUND OF THE INVENTION The present invention relates to actuatordrive circuits and more particularly to an actuator drive circuit forproducing a dual level driving current.

. two electrical coils is energized, the core is electromagneticallyattracted to and held inthe extreme position nearest the energizedelectrical coil. A helical spring is compressed between the end of theattracted core and an interior wall of the housing. When the core is tobe driven to the other extreme position, the first coil is deenergizedwhile the second coil is energized. Upon collapse of the electromagneticfield of the de-energized first coil, the stored mechanical force of thecompressed helical spring propels the core toward the second coil. Thecore is electromagneticallly attracted toward the second extremeposition by the energized second coil. The'core must be attracted to andheld against an opposing force exerted. by a second compressed helicalspring.

While the solenoid actuator described briefly above and in more detailin co-pending application Ser. No.

273,092 is capable of high performance; that performance can be realizedonly with unique drive circuitry. Conventional solenoid actuator drivecircuits produce a single level of drive current. While a relativelyhigh current level is needed to initially seat the core of the subjectactuator in either of its extreme positions, only a low holding currentis needed to hold the seated core against the opposing force exerted bythe compressed helical spring. A conventional drive circuit would haveto be designed to produce either a high or a low level of drive currentat all times. Drive circuitry producing high level drive current wouldprovide high speed performance but power requirements would be high. Thepower requirements in drive circuits producing low level current wouldbe low but the solenoid actuator would operate at a slower speed.

Moreover, the high speed characteristics of the subject actuator can berealized only if current decay in a de-energized coil occurs rapidlysince the electromagnetic field of a coil being de-energized would tendto retard core movement. Prior art solenoid drivers generally haveused'either relays or transistors in circuits employing a diode or RCnetwork across the deenergized coil to provide a path for decayingcurrent. An induced voltage spike occurring upon coil de-energizationcan set up relay arcs or can break down transistors. While speciallydesigned relays and high voltage transistors can be used to extend thelife cycle of the circuitry, these solutions add to the costof anysolenoid driving circuitry.

SUMMARY OF THE INVENTION circuits, drive circuitry which optimizesperformance of a solenoid actuator of the type described was invented.The drive circuitry included a pulse generating circuit which isconnected to a binary control signal source and which responds to anylogic level change in the control signal to generate a primary limitedduration pulse. A first logic circuit responds to the concurrence of aprimary limited duration pulse and a change in the control signal to afirst logic level to generate a first limited duration pulse. A secondlogic circuit similarly responds to the concurrence of the primarylimited duration pulse and a change in the control signal to a secondlogic level to generate a second limited duration pulse. Each of the twocoils in the solenoid actuator operates under the control of its owncurrent control circuit which includes a driving voltage source and aserially connected switching circuit for completing a current path fromthe voltage source through the coil when the control signal is at aspecific logic level. Each of the current control circuits also includesa low impedance bypass circuit connected to the output of one of thelogic circuits and in parallel with part of the asso ciated switchingcircuit. The bypass circuit effectively reduces the impedance of thecurrent path through the associated coil for the duration of the limitedduration pulse produced by the associated logic circuit. Thus, a high orseating current is applied to the coil as the core is attracted towardits extreme position and a low or holding current is applied once thecore is seated in that position.

DESCRIPTION OF THE DRAWINGS While the specification concludes withclaims particularly pointing out and distinctly claiming that which isregarded as the present invention, further details of one embodiment ofthe invention along with its further objects and advantages may be morereadily ascertained from the following detailed description when read inconjunction with the accompanying drawings wherein:

FIG. 1 is a block diagram of drive circuitry constructed in accordancewith the present invention; and

FIG. 2 is a more detailed schematic diagram of part of thecircuitryshown generally in FIG. 1.

DETAILED DESCRIPTION Referring to FIG. 1, the circuits shown in blockdiagram form control the energization of a first coil 10 and a secondcoil 12. The coils 10 and 12 are energized during mutually exclusive andcomplementary periods of time to attract a solenoid core (not shown) toopposite extreme positions in a solenoid housing. The logic level of abinary control signal applied at an input terminal 14 determines whichof the two coils is energized at any particular time. The binary controlsignal is applied to a first inverter 16. The inverted form of thebinary signal is then applied to a second inverter 18, to a pulse shaper20, to switching circuits 22 and 24 in current control circuitry 26associated with the first coil 10, and to one input of a logic AND gate28.

The output from the second inverter 18 is doubly inverted relative tothe original binary control signal and therefore is of the same sense.This output signal is applied to a pulse shaping circuit 30, toswitching circuits 32 and 34 in current controlling circuitry 36associated with the second coil 12 and to one input of a second AND gate38.

The outputsof the pulse shaping circuits 20 and 30 are applied to aconventional single shot circuit 40 which generates a primary limitedduration pulse when triggered by either of the pulse shaping circuits.That is, single shot 40 responds to any change in the logic level of thebinary control signal by generating a limited duration pulse. The outputof single shot 40 is applied to as a ground terminal hereafter. Theoutput of the AND gate 38 provides an input to a similar low impedancebypass circuit 46 paralleling the switching circuit 34 between the upperend of the second coil 12 and a reference or ground terminal 48.

In illustrating the operation of the system describe above, it isassumed that the second coil 12 is initially energized by a high levelbinary signal appearing on the input terminal 14. When the coil 12 is tobe deenergized and the coil energized, the binary control signal isswitched to a low level. The inverter 16 converts the low level binarycontrol signal to a high level signal which when applied to theswitching circuits 22 and 24 cuases those circuits to complete a currentpath from a voltage source 150 through the coil 10to the ground terminal44. Theinverter'18 produces a low level signal which triggers pulseshaping circuit 30 to I produce a limited duration trigger pulse for thesingle shot 40. The high level primary limited duration pulse producedby the single shot 40 is applied to the AND gate 28 along with the highlevel signal produced by the inverter 16. The output of the enabled ANDgate 28 enables the low impedance bypass circuit 42 for a limited periodof time immediately following the change of level of the binary controlsignal. The low impedance bypass circuit reduces the effective impedanceto curent ahigher impedance..As a result, the current applied to thecoil 10 is reduced to a'level'needed to hold the core of the associatedsolenoid in the extreme position. The current control circuitry 36associated with the second coil 12 operates in the same manner as thecirf plied to the single shot 40. The primary limited duration pulse onthe output of the single shot 40 is applied to the se'condinputs of theAND gates 28 and 38. AND gate 38 is enabled since its other input is there-inverted or high level signal produced by the inverter 18. Theenabled AND gate, 38 causes the low impedance bypass circuit 46'tobecome effective to provide a low imped-.

ance current path for coil 12. The re-inverted signal on the output ofinverter 18 causes switching circuits 32 and 34 to complete a currentpath for coil 12. Thus, when coil 12 is first re-energized, currentflows from the voltage source 52 through current switch 32, coil 12,switching circuit 34 and low impedance bypass 46 to the ground terminal48. After single shot 40 times out to inhibit AND gate 38, the lowimpedance bypass 46 is disabled causing allcurrent to flow through theswitching circuit 34. The removal of the low impedance bypass reducesthe level of current applied to the coil 12.

Referring to FIG. 2, elements which are common to both figures aredenoted by the same numerals. It can be seen that the pulse shapingcircuit 20 consists of a NPN transistor 54 having its emitter terminalconnected to ground, its base terminal connected to the output ofinverter 16 through a capacitor 54, and its collector terminal connectedto a positive voltage source 58 through a collector resistor 60. Thecollector terminal of the transistor 54 is connected to the input of aninverter 62, the output of which .provides one input to the single shot40. When the binary controlsignal on the input termina 14 is switched toa high'level, the inverted or negative going output of the inverter 16causes a negative going pulse to be applied to the capacitor 56. Theemitter tobase junction of the transis-j tor 54 becomes back biased andcauses the transistor 54 to be driven into non-conduction for a limitedtime;

pulse and thus the negative going pulse at the output of I inverter 62.

The pulse shaping circuit 30 similarly consists of an NPN transistor 64having its emitter terminal connected to ground, its base terminalcapacitively coupled to the output of the inverter 18 through acapacitor, and its collector terminal connected toia positive voltagesource 68 through a collector resistor 70. When the binary controlsignal applied to the input terminal l4 switches to a low level, thenegative going signal appearing on the output of inverter 18 causes anegative going voltageto be applied to the base terminal of thetransistor 64 through the capacitor 66. The transistor. 64 is driveninto non-conduction to provide a higher collector voltage at the inputto an inverter circuit 72. The inverter 72 provides a negative goingpulse which lasts until capacitor 66 charges to allow transistor 64 toresume conduction. When transistor 64 reenters a conductive state, thecollector voltage drops and the negative going output of the inverter 72returns to a normal level.

The switching circuit 22 may be seen'to consist of an NPN transistor 74having a grounded emitter terminal. The base terminal of the transistor74 isconnected to the output of inverter 16 through a pair of voltagelimiting diodes 76 and 78 and an oppositely poled diode 80.

The junction of the diodes 76 and 80 is connected through resistor 82 toa positive voltage source 84. The

collector terminal of the transistor 74 is coupled through resistor 86to the base terminal of a PNP transistor 88 having its emitter terminalconnected directly to the voltage source 50 and its collector terminalconnected to the upper end of the coil 10. The collector terminal of thetransistor 88 is also connected to the cathode of a diode 90 having itsanode connected to a negative voltage source 92.

While coil 12 is energized by a high level binary control signal on theinput terminal 14, the low level signal appearing on the output of theinverter 16 allows diode 80 to remain forward biased. The emitter tobase juncof the inverter 16 causes diode 80 to be back biased and diodes76 and 78 to be forward biased. The relatively more positive voltage atthe base terminal of the transistor 74 biases that transistor intoconduction, thereby reducing its collector voltage. The reducedcollector voltage causes the emitter to base junction of the transistor88'to become forward biased causing that transistor to be driven intoconduction, completing the current path from the voltage source 50through tran-' sistor-88 to the upper'end of coil 10.

The switching circuit 24 includes an NPN transistor 94 having itscollector terminal connected to the lower end of the coil through acurrent limiting resistor 96, its ernitter terminal connected directlyto the ground terminal 44, and its base terminal connected throughvoltage limiting diodes 98 and 100 and through oppositely poled diode102 to the output of the inverter 16. The common junction of diodes 98and 102 is connected to the lower end of a resistor 104 having its upperend connected to a positive voltage source 106. Switching circuit 24further includes a diode 95 having its anode connected to the lower endof coil 10 and its cathode connected to a positive voltage source 97.

When-the coil 10 is to be energized, the binary control signal on theinput terminal 14 is switched to a low logic level which drives thesignal on the output of the inverter 16 to a high'logic level. The highlogic level signal back biases diode 102 and allows the voltage source106 to forward bias the base to emitter junction of the transistor 94.Transistor 94, when conducting, and resistor 96 form a current pathbetween the lower end of coil 10 and the ground terminal 44. When coil10 is to be de-energized, the change in the binary control signal to ahigh logic level causes diode 102 to be forward biased and diodes98 and100 to be back biased which, in turn, causes the base to emitterjunction of the transis'tor 94 to be back biased. Transistor 94 isdriven into its non-conductive state to, open circuit the current pathwhich included thecurrent limiting resistor 96.

The low impedance bypass circuit 42 associated with coil '10 includes anNPN transistor 108 having its collector terminal connected to the lowerend of coil 10, its emitter terminal connected directly to the groundterminal 44, and its base terminal connected through a pair of voltagelimiting diodes 110 and 112 and an oppositely poled diode 114 to theoutput of the AND gate 28. The common junction of the diodes 112 and 114is connected to the lower end of a resistor 116 having its upper endconnected to a positive voltage source 118.

As was explained with reference to FIG. 1, the AND gate 28 is enabledfor a short period of time immediately following the energization of thecoil 10. During this limited period of time, the high logic level signalon the output of the AND gate 28 back biases the diode 114 to permit thevoltage source 118 to forward bias the base to emitter junction of thetransistor 108 through the diodes 110 and 112. When its base to emitterjunction is forward biased, the transistor 108 conducts to provide acurrent path parallel to the current path formed by the transistor 94and the current limiting resistor 96 in the switching circuit 24. Theparallel current path reduces the impedance to current flow andconsequently results in a higher level of current through the coil 10 aslong as transistor 108 conducts.

When single shot 40 times out, AND gate 28 is inhibited and its outputdrops to a low logic level. The low logic level signal causes diode 114to be forward biased, allowing diodes 110 and 112 to be back biased. Asa result, the transistor 108 is driven into nonconduction, opencircuiting the low impedance bypass. Since all current is divertedthrough the current limiting resistor 96 and a transistor 94 once thelow impedance bypass is rendered ineffective, the effective impedance ofthe coil is increased, thereby reducing the level of current applied tothe coil 10. This lower level of current is maintained as long as coil10 is energized.

To optimize the performance of the actuator when one coil is energizedas the other coil is de-energiz ed, the current in the formerlyenergized coil must be made to decay rapidly so that the remanentelectromagnetic field of the coil being de-energized will not retard theacceleration of the core toward the extreme position adjacent the newlyenergized coil. When coil 10 is energiz ed, the conduction through thetransistors 88 and 94 cause the diodes and to be back biased relative tothe voltage sources 92 and 97 respectively. When, however, coil 10 isde-energized by driving transistors 88 and 94 into their non-conductivestates, the voltage induced across coil 10 causes the diodes 90 and 92to become forward biased. The forward biasing of these diodes causes thevoltage across coil 10 to be limited to the negative and positive valuesof the voltages produced by the voltage sources 92 and 97 respectively.An initial voltage of 2V is impressed across coil 10 immediately uponde-energization, causing the initial current rate of decay of the coilcurrent to be 2V/L where L is the inductance of the coil.

The drive circuitry for thesecond coil 12 is identical to that for thefirst coil 10 and differs only in that it operates in a complementarymanner. For that reason, drive circuitry for coil 12 is shown only as ablock 120 in FIG. 2.

While there has been described what is thought to be a preferredembodiment of the present invention, modifications and variations willoccur to those skilled in the art once they become familiar with theinvention. Therefore, it is intended that the appended claims shall beconstrued as including all such variations and modifications as fallwithin the true spirit and scope of the invention.

We claim:

1. Drive circuitry for a solenoid actuator having first and second coilsenergizable during mutually exclusive.

and complementary periods of time as a function of the level of a binarycontrol signal including:

a. a pulse generating circuit connected to the binary control signalsource and responsive to any logic level change in the control signal togenerate a primary limited duration pulse;

b. a first logic circuit connected to the output of the pulse generatingcircuit and in circuit with the control signal source to generate afirst limited duration pulse only when the control signal changes to afirst logic level;

c. a second logic circuit connected to the output of the pulsegenerating circuit and in circuit with the control signal source togenerate a second limited duration pulse only when the binary controlsignal changes to a second logic level;

d. a first current control circuit for the first coil comprising i. afirst driving voltage source, ii. a first switching circuit connected inseries with the first driving voltage source and the first coil,

said switching circuit being responsive to the control signal being atits first level to complete a current path from the voltage sourcethrough the first coil, and

iii. a first low impedance bypass circuit connected to theoutput of thefirst logic circuit and in paral- .lel with part of the switchingcircuit to reduce the ,impedanceof the completed current path'for theduration of the first limited duration pulse; e. a second currentcontrol circuit for the second coil comprising 7 I i.-a"second drivin'gvoltage source,

ii, a second switching circuit connected in series with the seconddriving voltage and the second coil, saidswitching circuit beingresponsive to the control signal being at its second level to complete acurrent path from the voltage source through the second coil, and

iii. a second low impedance bypass circuit connected tothe output of thesecond logic circuit and in parallel with part of. the second switchingcircuit to reduce the impedance of the completed current path for theduration of the. second limited duration pulse. l I I v 2. A controlcircuit as recited in claim l-wherein each of said first and seconddriving voltage sources has a first polarity and each of said first andsecond switching circuits further includes:

a. a decay voltage source having a second polarity;

b. a first diode having one terminal connected to the end of the'coiladjacent said driving voltage source and the other terminal connected tothe decay voltage, source, said first diode being normally back biased;r

c. a seconddiode having one terminal connected to' the other' endlof'the coil and the other terminal connected to the driving voltage source,said second diode also being normally back biased;

d. said first and second diodes being forward biased by the voltageinduced across the coil immediately following coil deenergization.

3. A control circuit as recited in claim 1 wherein each of said firstand second switching circuits further comprises:

a. a first transistor having its emitter and collector terminalsconnected in series between the driving voltage source and one end ofthe associated coil and its base terminal connected in circuit with thebinary control signal source; o

b; an impedance connected in series at the other end of the coil; and

c. a second transistor having its emitter and collector terminalsconnected in series between the other end of the coil and a referencevoltage terminal and its base terminal connected in circuit with theassociated logic circuit.

4. A control circuit as recited in claim 2 wherein each of said firstand second switching circuits further comprises: v p I a. a firsttransistor having its emitter and collector terminals connected inseries between the driving voltage source and one end of the associatedcoil and its base terminal connected in-circuit with the binary controlsignal source; I Y

b. an impedance connected in series at the other end of the coil; and Ia c. a second transistor having its emitter andcollector terminalsconnected in series be'tweenthe lower end of the impedance and areference voltage terminal and its base terminal connected in circuitwith the binary control signal source. I I

5. A control circuit as recited in claim 3 wherein each of said lowimpedance bypass circuits comprises a third transistor having itsemitter and collector terminals connected in series between saidotherxend of said coil and the reference voltage terminal and its baseterminal connected to the output of the associated logic circuit,

said third transistor being biased into conduction for the duration ofthe limited duration pulseproduced by said associated logic circuit.

6. A control circuit as recited in claim 4 wherein each of saidlowimpedance bypass circuits comprises a third transistor having itsemitter and collector terminals connected in series between said otherend of said coil and the reference voltage terminal and its baseterminal connected to the output of the associated logic circuit, saidthird transistor being biased into conduction for the duration of thelimited duration pulse produced by said associated logic circuit.

1. Drive circuitry for a solenoid actuator having first and second coilsenergizable during mutually exclusive and complementary periods of timeas a function of the level of a binary control signal including: a. apulse generating circuit connected to the binary control signal sourceand responsive to any logic level change in the control signal togenerate a primary limited duration pulse; b. a first logic circuitconnected to the output of the pulse generating circuit and in circuitwith the control signal source to generate a first limited durationpulse only when the control signal changes to a first logic level; c. asecond logic circuit connected to the output of the pulse generatingcircuit and in circuit with the control signal source to generate asecond limited duration pulse only when the binary control signalchanges to a second logic level; d. a first current control circuit forthe first coil comprising i. a first driving voltage source, ii. a firstswitching circuit connected in series with the first driving voltagesource and the first coil, said switching circuit being responsive tothe control signal being at its first level to complete a current pathfrom the voltage source through the first coil, and iii. a first lowimpedance bypass circuit connected to the output of the first logiccircuit and in parallel with part of the switching circuit to reduce theimpedance of the completed current path for the duration of the firstlimited duration pulse; e. a second current control circuit for thesecond coil comprising i. a second driving voltage source, ii. a secondswitching circuit connected in series with the second driving voltagesource and the second coil, said switching circuit being responsive tothe control signal being at its second level to complete a current pathfrom the voltage source through the second coil, and iii. a second lowiMpedance bypass circuit connected to the output of the second logiccircuit and in parallel with part of the second switching circuit toreduce the impedance of the completed current path for the duration ofthe second limited duration pulse.
 2. A control circuit as recited inclaim 1 wherein each of said first and second driving voltage sourceshas a first polarity and each of said first and second switchingcircuits further includes: a. a decay voltage source having a secondpolarity; b. a first diode having one terminal connected to the end ofthe coil adjacent said driving voltage source and the other terminalconnected to the decay voltage source, said first diode being normallyback biased; c. a second diode having one terminal connected to theother end of the coil and the other terminal connected to the drivingvoltage source, said second diode also being normally back biased; d.said first and second diodes being forward biased by the voltage inducedacross the coil immediately following coil deenergization.
 3. A controlcircuit as recited in claim 1 wherein each of said first and secondswitching circuits further comprises: a. a first transistor having itsemitter and collector terminals connected in series between the drivingvoltage source and one end of the associated coil and its base terminalconnected in circuit with the binary control signal source; b. animpedance connected in series at the other end of the coil; and c. asecond transistor having its emitter and collector terminals connectedin series between the other end of the coil and a reference voltageterminal and its base terminal connected in circuit with the associatedlogic circuit.
 4. A control circuit as recited in claim 2 wherein eachof said first and second switching circuits further comprises: a. afirst transistor having its emitter and collector terminals connected inseries between the driving voltage source and one end of the associatedcoil and its base terminal connected in circuit with the binary controlsignal source; b. an impedance connected in series at the other end ofthe coil; and c. a second transistor having its emitter and collectorterminals connected in series between the lower end of the impedance anda reference voltage terminal and its base terminal connected in circuitwith the binary control signal source.
 5. A control circuit as recitedin claim 3 wherein each of said low impedance bypass circuits comprisesa third transistor having its emitter and collector terminals connectedin series between said other end of said coil and the reference voltageterminal and its base terminal connected to the output of the associatedlogic circuit, said third transistor being biased into conduction forthe duration of the limited duration pulse produced by said associatedlogic circuit.
 6. A control circuit as recited in claim 4 wherein eachof said low impedance bypass circuits comprises a third transistorhaving its emitter and collector terminals connected in series betweensaid other end of said coil and the reference voltage terminal and itsbase terminal connected to the output of the associated logic circuit,said third transistor being biased into conduction for the duration ofthe limited duration pulse produced by said associated logic circuit.